A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design

This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3 × 3 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 μW under a network environment. key words: cross-layer design, sensor networks, sensor node, MAC protocol, time synchronization, low power